Circuit for clock signal extraction from a high speed data stream

Schaltung zur Taktsignalgewinnung aus einem Hochgeschwindigkeitsdatenstrom

Circuit pour la récupération d'horloge d'un train de données à haute vitesse


The circuit for clock signal extraction from a high speed data stream allows a rapid attainment of the identity between the frequencies of the locally generated clock signal and of the data signal, even when such frequencies are very different. The circuit can easily be inserted into a more complex CMOS digital integrated circuit, it has low power dissipation and is capable of operating at bit rates exceeding 300 Mbit/s. The circuit comprises a main phase locked loop, which controls a voltage controlled oscillator by continually controlling its phase, and a secondary loop, which allows the main loop to become locked, by causing the voltage controlled oscillator to oscillate at a frequency close to the operating frequency.




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Patent Citations (1)

    Publication numberPublication dateAssigneeTitle
    GB-2265284-ASeptember 22, 1993Korea Electronics Telecomm, Korea TelecommunicationBit synchroniser for nrz data

NO-Patent Citations (0)


Cited By (5)

    Publication numberPublication dateAssigneeTitle
    EP-0881773-A1December 02, 1998Sun Microsystems Inc.Frequenzdifferenzdetektor für NRZ-Signal
    EP-1912333-A1April 16, 2008QUALCOMM IncorporatedBoucle à verrouillage de phase qui règle automatiquement le gain
    GB-2360152-ASeptember 12, 2001Rover Group, Bayerische Motoren Werke AgControl circuit arrangements
    US-6020765-AFebruary 01, 2000Sun Microsystems, Inc.Frequency difference detector for use with an NRZ signal
    US-7825706-B2November 02, 2010Qualcomm IncorporatedPhase locked loop that sets gain automatically