半导体装置

Abstract

本发明提供一种用于通过缓和SJ柱与漂移区之间的电场集中,而在一块半导体芯片内将MOSFET区、FWD区和IGBT区电连接且并联连接的最佳结构。本发明提供的半导体装置,具备:半导体基板;具有第一柱和第二柱的重复结构的超结型MOSFET部;在半导体基板与超结型MOSFET部分离而设置,并具有包括第二导电型的杂质的漂移区的并列器件部;在半导体基板并位于超结型MOSFET部与并列器件部之间的边界部,其中,边界部从一个主表面侧向另一主表面侧延伸,并且至少具有一个具有第一导电型的杂质的第三柱,第三柱比第一柱和第二柱都浅。
To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by mitigating electric field concentration between a SJ column and a drift region, a semiconductor device is provided, the semiconductor device including: a semiconductor substrate: a super junction MOSFET having a repetitive structure of a first column and a second column; a parallel device having a drift region including second conductivity-type impurities, and being provided separately from the super junction MOSFET in the semiconductor substrate; and a boundary portion located between the super junction MOSFET and the parallel device in the semiconductor substrate, wherein the boundary portion extends from one main surface side to the other main surface side, and has at least one third column having first conductivity-type impurities, and the third column is shallower than the first column and the second column.

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